Darn! Typo in vc90 project file

diff --git a/projects/VC90/SimGear.vcproj b/projects/VC90/SimGear.vcproj
index ba0a524f2eb08f9bdfa6df3938ce634ba984ebd6..8726c70ff5531786c31ae6d8486cfe4b0ba95ab7 100644 (file)
--- a/projects/VC90/SimGear.vcproj
+++ b/projects/VC90/SimGear.vcproj
@@ -1018,6 +1018,7 @@
                        <File\r
                                RelativePath="..\..\simgear\props\tiedpropertylist.hxx"\r
                                >\r
+                       </File>\r
                        <File\r
                                RelativePath="..\..\simgear\props\props.cxx"\r
                                >\r